1. Field of the Invention
The present invention relates to a semiconductor device such as an application specific integrated circuit (ASIC), and more particularly, to capacitors and resistors having a metal-insulator-metal (MIM) structure.
2. Description of the Related Art
Generally, in ASIC semiconductor devices, a large number of semiconductor transistor circuits, capacitors and resistors are connected to each other in accordance with the customer's request. ASIC semiconductor devices are divided into cell-based ASIC semiconductor devices, master slice type ASIC semiconductor devices and the like. The master slice type ASIC semiconductor devices are disclosed in JP-2000-307062A.
On the other hand, structured ASIC semiconductor devices have been developed to reduce the turn around time and the manufacturing cost.
A prior art structured ASIC semiconductor device is constructed by a common-use section where basic logic cells (semiconductor transistor circuits), power supply lines, basic logic cell connections, macro connections and the like are formed, and a customized section where input/output connections and conductive pattern layers for the basic logic cells are formed. In this case, the common-use section is formed regardless of the customer's request, while the customized section is formed in accordance with the customer's request.
Also, passive elements such as metal-insulator-metal (MIM) capacitors and MIM resistors are disclosed in JP-2004-193602A, WO02/17367A2 and U.S. Patent Application Publication No. 2005/0082639 A1.
Particularly, referring to U.S. Patent Application Publication No. 2005/0082639 A1, in order to realize an MIM capacitor and an MIM resistor, triple-stacked structures each including one lower electrode layer, one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer are provided.